CITS4407 Open Source Tools and Scripting  
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Variable substitutions in make, continued

As our projects grow, we add more C source files to the project. We should refactor our Makefiles when we notice common patterns: 


# A Makefile to build our 'calcmarks' project

PROJECT =  calcmarks
HEADERS =  $(PROJECT).h
OBJ     =  calcmarks.o globals.o readmarks.o correlation.o


C99     =  cc -std=c99
CFLAGS  =  -Wall -pedantic -Werror


$(PROJECT) : $(OBJ)
       $(C99) $(CFLAGS) -o $(PROJECT) $(OBJ) -lm


calcmarks.o : calcmarks.c $(HEADERS)
       $(C99) $(CFLAGS) -c calcmarks.c

globals.o : globals.c $(HEADERS)
       $(C99) $(CFLAGS) -c globals.c

readmarks.o : readmarks.c $(HEADERS)
       $(C99) $(CFLAGS) -c readmarks.c

correlation.o : correlation.c $(HEADERS)
       $(C99) $(CFLAGS) -c correlation.c


clean:
       rm -f $(PROJECT) $(OBJ)

Of note:
  • we have introduced a new variable, $(PROJECT), to name our project,
  • we have introduced a new variable, $(OBJ), to collate all of our object files,
  • our project specifically depends on our object files,
  • we have a new target, named clean, to remove all unnecessary files. clean has no dependencies, and so will always be executed if requested.

 

CITS4407 Open Source Tools and Scripting, Week 9, p9.