CITS4407 Open Source Tools and Scripting  
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Variable substitutions in make

As we see from the previous example, Makefiles can themselves become long, detailed files, and we'd like to "factor out" a lot of the common information.
It's similar to setting constants in C, with #define

Although not a full programming language, make supports simple variable definitions and variable substitutions. 


# A Makefile to build our 'calcmarks' project

C99     =  cc -std=c99
CFLAGS  =  -Wall -pedantic -Werror


calcmarks : calcmarks.o globals.o readmarks.o correlation.o
       $(C99) $(CFLAGS) -o calcmarks \
                  calcmarks.o globals.o readmarks.o correlation.o -lm


calcmarks.o : calcmarks.c calcmarks.h
       $(C99) $(CFLAGS) -c calcmarks.c

globals.o : globals.c calcmarks.h
       $(C99) $(CFLAGS) -c globals.c

readmarks.o : readmarks.c calcmarks.h
       $(C99) $(CFLAGS) -c readmarks.c

correlation.o : correlation.c calcmarks.h
       $(C99) $(CFLAGS) -c correlation.c

Of note:
  • variables are usually defined near the top of the Makefile.
  • the variables are simply expanded in-line with $(VARNAME).
  • warning - the syntax of make's variable substitutions is slightly different to those of our standard shells.

 

CITS4407 Open Source Tools and Scripting, Week 9, p8.