Employing automatic variables in a Makefile
We further note that each of our object files
depends on its C source file,
and that it would be handy to reduce these very common lines.
make provides
a (wide) variety of filename patterns and
automatic variables
to considerably simplify our actions:
# A Makefile to build our 'calcmarks' project
PROJECT = calcmarks
HEADERS = $(PROJECT).h
OBJ = calcmarks.o globals.o readmarks.o correlation.o
C99 = cc -std=c99
CFLAGS = -Wall -pedantic -Werror
$(PROJECT) : $(OBJ)
$(C99) $(CFLAGS) -o $(PROJECT) $(OBJ) -lm
%.o : %.c $(HEADERS)
$(C99) $(CFLAGS) -c $<
clean:
rm -f $(PROJECT) $(OBJ)
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Of note:
- the pattern %.o matches, in turn,
each of the 4 object filenames to be considered,
- the pattern %.c is "built" from the C file corresponding to the
%.o file, and
- the automatic variable $< is "the reason we're here".
make supports
many automatic variables,
which it "keeps up to date" as its execution proceeds:
| $@ | This will always expand to the current target.
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| $< | The name of the first dependency. This is the first item listed
after the colon.
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| $? | The names of all the dependencies that are newer than the target.
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Fortunately, we rarely need to remember all of these patterns and variables,
and generally just copy and modify existing Makefiles.
CITS4407 Open Source Tools and Scripting, Week 9, p10.
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CITS4407