Variable substitutions in make, continued
As our projects grow,
we add more C source files to the project.
We should refactor our Makefiles when we notice common patterns:
# A Makefile to build our 'calcmarks' project
PROJECT = calcmarks
HEADERS = $(PROJECT).h
OBJ = calcmarks.o globals.o readmarks.o correlation.o
C11 = cc -std=c11
CFLAGS = -Wall -Werror
$(PROJECT) : $(OBJ)
$(C11) $(CFLAGS) -o $(PROJECT) $(OBJ) -lm
calcmarks.o : calcmarks.c $(HEADERS)
$(C11) $(CFLAGS) -c calcmarks.c
globals.o : globals.c $(HEADERS)
$(C11) $(CFLAGS) -c globals.c
readmarks.o : readmarks.c $(HEADERS)
$(C11) $(CFLAGS) -c readmarks.c
correlation.o : correlation.c $(HEADERS)
$(C11) $(CFLAGS) -c correlation.c
clean:
rm -f $(PROJECT) $(OBJ)
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Of note:
- we have introduced a new variable,
PROJECT,
to name our project,
- the value of the new variable,
HEADERS
is defined by accessing the value of
$(PROJECT),
- we have introduced a new variable,
OBJ,
to collate all of our object files,
- our project specifically depends on our object files,
- we have a new target, named clean,
to remove all unnecessary files. clean has no dependencies,
and so will always be executed if requested.
CITS2002 Systems Programming, Lecture 17, p14, 26th September 2023.
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CITS2002